The present invention relates to a method for manufacturing a highly integrated semiconductor memory device. More particularly, the present invention relates to a method for manufacturing a semiconductor memory device provided with a trophy-shaped landing pad formed by a multiple-step etching process and a contact hole with a high aspect ratio.
The design rule for highly integrated memory devices reduces gradually from about a 1 mm level in the generation of 1 Mbit-grade dynamic random access memory ("DRAM") devices to about a 0.15 mm level in the generation of 1 Gbit-grade DRAM devices. Thus, a contact hole, which provides an electrical contact part with respect to the silicon layer, diminishes gradually in dimension. Furthermore, the aspect ratio of the contact hole tends to gradually increase in accordance with the use of three dimensional capacitor structures in the vertical direction. The decrease of the contact hole's diameter and its high aspect ratio impose a large burden on succeeding photolithography steps. If the photolithography is carried out without accurate alignment, the contact hole cannot be formed at a desired site. Also, in the case of a high aspect ratio, it is likely that the etching process of the contact hole will cease before the interlayer insulation film is entirely removed.
A conventional DRAM having a capacitor over bitline ("COB") structure will be explained as an example. With the decrease of a dimension of a buried contact ("BC") and an increase in the aspect ratio, a technique has been proposed for forming a stable BC by using a landing pad without performing the etching process of the BC to secure an alignment margin for the photolithography. This proposal was for a product using the 64M DRAM-grade design rule. In general, the technique uses a single process to simultaneously form a bit line landing pad for a connection to the bit line and a storage node landing pad for a connection to the storage node. This diminishes the required etching depth in the etching process at the time of forming the BC and secures the desired alignment margin in the etching process.
However, a gap between the landing pads diminishes to approximately 0.1 mm according to a further limitation of the design rule resulting from the increase of the degree of integration. This makes it substantially difficult to restrain the occurrence of a stringer or a bridge phenomenon. In order to restrain the stringer and the bridge phenomenon resulting from the limitation of the design rule, a method has been proposed in which only the landing pad for the bit line is chiefly formed and a BC for the storage node is directly connected to the active region of a semiconductor substrate by self-aligning.
FIG. 1 shows a DRAM cell equipped with the BC for the bit line formed on the landing pad and the BC for the storage node using self-alignment, according to the method described above. As shown in FIG. 1, the DRAM cell includes a transistor 2, a landing pad 13, a first interlayer insulation film 15, a bit line 17 connected to the landing pad 13 and passing through the first interlayer insulation film 15, a second interlayer insulation film 19, a second side wall spacer 21, and a storage node 23.
The transistor 2 includes a gate oxide film 3, a gate, an insulation film 9, a first side wall spacer 11, and a source/drain region (not shown). The gate oxide film 3 is formed on a semiconductor substrate 1. The gate is a polyside structure in which a polycrystalline silicon 5 doped with impurities and a silicide 7 are layered. The insulation film 9 acts to cap the gate. The source/drain region is formed on substrate 1 between the gate patterns.
The landing pad 13 is for a bit line formed between the gates of the transistor. The first interlayer insulation film 15 is formed on the whole surface of the resultant structure. The second interlayer insulation film 19 is also deposited on the whole surface of the resultant structure. The second side wall spacer 21 acts to protect the side wall of the contact hole passing through first and second interlayer insulation films 15 and 19. The storage node 23 is connected to the source/drain region of the transistor through the contact hole.
When a BC is formed for a 1 Gbit-grade DRAM by using the conventional method as described above, however, the etching process ceases before the interlayer insulation films 15 and 17 are removed. This happens because the aspect ratio must be six or more according to the design rules for the 1 Gbit-grade DRAM. As a result of this limitation, the contact hole is not opened perfectly. Also, the required alignment margin for the photolithography is not secured because no landing pad is provided between the BC for the storage node and the semiconductor substrate.